1. Field of the Invention
The invention relates to a shallow trench isolation (STI) in a semiconductor substrate and a method of forming the same, and more particularly to a shallow trench isolation where recesses are not formed at a surface of an oxide film filled in a trench formed in a semiconductor substrate, and method of forming such a shallow trench isolation.
2. Description of the Related Art
When devices formed on a semiconductor substrate have to be electrically isolated from one another, those skilled in the art often select shallow trench isolation (hereinbelow, referred so simply as xe2x80x9cSTIxe2x80x9d) where a trench is formed at a surface of a semiconductor substrate and the trench is filled with an insulating film.
FIGS. 1A to 1G are cross-sectional views of STI fabricated by a conventional method.
First, as illustrated in FIG. 1A, a trench mask pattern 16 comprised of a silicon dioxide film 12 formed by thermal oxidation and a silicon nitride film 14 is formed on a semiconductor substrate such as a silicon substrate 10.
Then, as illustrated in FIG. 1B, the silicon substrate 10 is etched by dry etching through the use of the mask pattern 16 to thereby form a trench 18.
Then, as illustrated in FIG. 1C, the silicon substrate 10 is thermally oxidized to thereby form a silicon dioxide film 20 covering a bottom and a sidewall of the trench 18.
Then, as illustrated in FIG. 1D, a silicon dioxide film 22 is formed over the product illustrated in FIG. 1C such that the trench 18 is entirely filled with the silicon dioxide film 22.
Then, as illustrated in FIG. 1E, the silicon dioxide film 22 is polished by chemical mechanical polishing (CMP) until the silicon nitride film 14 appears. That is, the silicon nitride film 14 is used as a polishing stopper.
Then, as illustrated in FIG. 1F, the silicon nitride film 14 is removed by wet etching.
Then, as illustrated in FIG. 1G, the silicon dioxide film 12 and a portion of the silicon dioxide film 22 are removed by wet etching such that the silicon dioxide film 22 is on a level with the silicon substrate 10.
Thus, there is completed STI wherein the trench is filled with the silicon dioxide film 22.
Since the wet etching is isotropically carried out in the step illustrated in FIG. 1G, a portion 24 (see FIG. 1F) at which a sidewall of the silicon dioxide film 22 meets the silicon dioxide film 12 is most aggressively etched. As a result, as illustrated in FIG. 1G, recesses 26 are formed at a surface of the silicon dioxide film 22 filling the trench 28 therewith.
For instance, when the silicon dioxide film 22 has a depth in the range of 300 to 400 nm, the recesses 26 would have a depth of about 50 nm.
In the above-mentioned conventional method of fabricating STI, it is unavoidable that the recesses 26 are formed at a surface of the silicon dioxide film 22 filling the trench 18 therewith. The recesses 26 cause a problem as follows.
It is assumed that MOSFET is fabricated on the silicon substrate 10. If a gate electrode of MOSFET is formed on STI, the recess 26 creates regions of high electric field at corners of the recess 26, and hence, a threshold voltage at the corners of the recess 26 is reduced. This results in hump or kink phenomenon in the Id-Vg characteristic of MOSFET, further resulting in poor performance of MOSFET.
Such a problem as mentioned above is indicated in the following documents, for instance:
(A) C. Chen et al., 1996 IEDM Tech. Digest, pp 837-840;
(B) H. Perera et al., 1995 IEDM Tech. Digest, pp 679-682; and
(C) M. Nandakumar et al., 1998 IEDM Tech. Digest, pp 133-136.
In addition, if the recesses 26 had an extremely great depth, etching residue would remain when a gate electrode is etched, resulting in a problem of shortcircuit between gate wirings.
Many attempts have been made to fabricate STI where recesses are not formed at a surface of a silicon dioxide film filling a trench therewith.
For instance, a method in which a silicon dioxide film filling a trench therewith is T-shaped such that ends of the silicon dioxide film are located outside a trench has been suggested in the following documents:
(A) P. C. Fazan et al., 1993 IEDM Tech. Digest, pp 57-60;
(B) W. K. Yeh et al., 1998 SSDM, pp 98-99;
(C) T. Park et al., 1996 IEDM Tech. Digest, pp 675-678;
(D) A. Chatterjee et al., 1996 IEDM Tech. Digest, pp 829-832; and
(E) T. Yamazaki et al., 1999 SSDM, pp 18-19.
A method in which a trench is formed after a gate electrode has been formed is suggested in the following document:
(F) C. Chen et al., 1996 IEDM Tech. Digest, pp 837-840.
However, it is not always possible even by the above-mentioned methods to perfectly prevent formation of the recesses 26 at a surface of the silicon dioxide film 22.
In the conventional method of fabricating STI, having been explained with reference to FIGS. 1A to 1G, the silicon dioxide film 22 illustrated in FIG. 1D may be thermally annealed at a temperature equal to or greater than 1000 degrees centigrade to densify the silicon dioxide film 22 in order to enhance a resistance of the silicon dioxide film 22 against wet etching, or reduce an etching rate of the silicon dioxide film 22 for preventing the formation of the recesses 26.
However, if the silicon dioxide film 22 were thermally annealed, the silicon dioxide film 22 would be contracted, resulting in that stresses are generated in the silicon substrate 10, and hence, crystal defects are generated. If the silicon dioxide film 22 were thermally annealed at about 800 degrees centigrade so that small stresses are generated in the silicon substrate 10, it would be impossible to enhance a resistance of the silicon dioxide film 22 to etching.
In view of the above-mentioned problems in the conventional methods, it is an object of the present invention to provide a method of fabricating a shallow trench isolation which is capable of preventing the formation of recesses at a surface of an oxide film filling a trench therewith, and further preventing generation of stresses in a semiconductor substrate.
It is also an object of the present invention to provide a shallow trench isolation which is capable of doing the same.
In one aspect, there is provided a method of forming a shallow trench isolation, including the steps, in sequence, of (a) forming a trench in a semiconductor substrate, (b) forming a first oxide film covering an inner surface of the trench such that the trench is not filled with the first oxide film, (c) heating the first oxide film, (d) forming a second oxide film over a product resulted from the step (c) such that the trench is filled with the second oxide film, and (e) etching the first and second oxide films such that the first and second oxide films are on a level with a surface of the semiconductor substrate.
In accordance with the present invention, an oxide film filling a trench therewith is designed to have a two-layered structure including the first oxide film and the second oxide film. The first oxide film is designed to have such a thickness that a trench is not filled with the first oxide film. That is, the first oxide film is formed in the step (b) to have a thickness smaller than a half of a width of the trench. The first oxide film is then heated to be densified and have an enhanced resistance to etching. Though the first oxide film is contracted in the heating step (c), a contract stress is absorbed into the first oxide film, because a space exists adjacent to the first oxide film in the trench. Hence, there is not generated a stress in the semiconductor substrate.
It is preferable that the first oxide film is heated in the step (c) at a temperature equal to or greater than 900 degrees centigrade in order to enhance a resistance of the first oxide film to etching. It is also preferable that the first oxide film is heated in the step (c) at a temperature equal to or smaller than 1200 degrees centigrade in order to prevent curvature of the semiconductor substrate.
Then, the second oxide film is formed over the first oxide film in the step (d) such that the trench is filled with the second oxide film. Then, the first and second oxide films are etched in the step (e) such that the first and second oxide films are on a level with a surface of the semiconductor substrate. Since the first oxide film has a smaller etching rate than an etching rate of the semiconductor substrate, a portion at which a sidewall of the first oxide film meets a surface of the semiconductor substrate is slowly etched. Accordingly, unlike the conventional method illustrated in FIGS. 1A to 1G, recesses are not formed at a surface of the second oxide film.
For instance, the first and second silicon dioxide films may be comprised of a high-density plasma chemical vapor deposition (HDP-CVD) film, a tetraethylorthosilicate non-doped silicate glass (TEOSNSG) film, a O3-TEOSNSG film, a high temperature oxide (HTO) film, or a spin on glass (SOG) film.
In particular, a HDP-CVD film is a most preferable film because it has a smallest etching rate among the above-mentioned films. Since other films such as a TEOSNSG film have a high etching rate in as-depo condition, when the first and second oxide films are comprised of such other films, it would be necessary to heat the second oxide film as well as the first oxide film in order to reduce an etching rate of the second oxide film to prevent formation of recesses at a surface of the second oxide film.
It is preferable that the method further includes the step of (f) forming a third oxide film covering a bottom and a sidewall of the trench therewith, the step (f) being to be carried out between the steps (a) and (b), and that the method still further includes the step of (g) forming a nitride film covering the third oxide film thereover, the step (g) being to be carried out between the steps (f) and (b).
The third oxide film and the nitride film prevent the semiconductor substrate from being oxidized around the trench, when the first oxide film is heated. This ensures that the first oxide film may be heated for a longer time, and may be heated at a temperature higher than a temperature at which the first oxide film is heated without the nitride film being formed.
There is further provided a method of forming a shallow trench isolation, including the steps, in sequence, of (a) forming a trench in a semiconductor substrate, (b) forming a first oxide film covering an inner surface of the trench such that the trench is not filled with the first oxide film, (c) heating the first oxide film, (d) forming a second oxide film over a product resulted from the step (c) such that the trench is filled with the second oxide film, (e) heating the second oxide film, and (f) etching the first and second oxide films such that the first and second oxide films are on a level with a surface of the semiconductor substrate.
It is preferable that the second oxide film is heated in the step (e) at a temperature in the range of 900 to 1200 degrees centigrade both inclusive, in which case it is preferable that the second oxide film is heated in the step (e) at a temperature smaller than a temperature at which the first oxide film is heated.
There is still further provided a method of forming a shallow trench isolation, including the steps, in sequence, of (a) forming a mask pattern on a semiconductor substrate, the mask pattern being comprised of an oxide layer and a nitride layer, (b) forming a trench in the semiconductor substrate with the mask pattern being used as a mask, (c) forming a first oxide film covering an inner surface of the trench such that the trench is not filled with the first oxide film, (d) heating the first oxide film, (e) forming a second oxide film over a product resulted from the step (d) such that the trench is filled with the second oxide film, (f) polishing the first and second oxide films through the use of the nitride layer as a stopper, (g) etching the nitride layer for removal, and (h) etching the first and second oxide films such that the first and second oxide films are on a level with a surface of the semiconductor substrate.
There is yet further provided a method of forming a shallow trench isolation, including the steps, in sequence, of (a) forming a mask pattern on a semiconductor substrate, the mask pattern being comprised of an oxide layer and a nitride layer, (b) forming a trench in the semiconductor substrate with the mask pattern being used as a mask, (c) forming a first oxide film covering an inner surface of the trench such that the trench is not filled with the first oxide film, (d) heating the first oxide film, (e) forming a second oxide film over a product resulted from the step (d) such that the trench is filled with the second oxide film, (f) heating the second oxide film, (g) polishing the first and second oxide films through the use of the nitride layer as a stopper, (h) etching the nitride layer for removal, and (i) etching the first and second oxide films such that the first and second oxide films are on a level with a surface of the semiconductor substrate.
There is still yet further provided a method of forming a shallow trench isolation, including the steps, in sequence, of (a) forming a mask pattern on a silicon substrate, the mask pattern being comprised of a silicon dioxide layer and a silicon nitride layer, (b) forming a trench in the silicon substrate with the mask pattern being used as a mask, (c) forming a first silicon dioxide film covering an inner surface of the trench such that the trench is not filled with the first silicon dioxide film, (d) heating the first silicon dioxide film, (e) forming a second silicon dioxide film over a product resulted from the step (d) such that the trench is filled with the second silicon dioxide film, (f) polishing the first and second silicon dioxide films through the use of the silicon nitride layer as a stopper, (g) etching the silicon nitride layer for removal, and (h) etching the first and second silicon dioxide films such that the first and second silicon dioxide films are on a level with a surface of the silicon substrate.
There is further provided a method of forming a shallow trench isolation, including the steps, in sequence, of (a) forming a mask pattern on a silicon substrate, the mask pattern being comprised of a silicon dioxide layer and a silicon nitride layer, (b) forming a trench in the silicon substrate with the mask pattern being used as a mask, (c) forming a first silicon dioxide film covering an inner surface of the trench such that the trench is not filled with the first silicon dioxide film, (d) heating the first silicon dioxide film, (e) forming a second silicon dioxide film over a product resulted from the step (d) such that the trench is filled with the second silicon dioxide film, (f) heating the second silicon dioxide film, (g) polishing the first and second silicon dioxide films through the use of the silicon nitride layer as a stopper, (h) etching the silicon nitride layer for removal, and (i) etching the first and second silicon dioxide films such that the first and second silicon dioxide films are on a level with a surface of the silicon substrate.
In another aspect of the present invention, there is provided a shallow trench isolation including (a) a semiconductor substrate formed at a surface thereof with a trench, (b) a first oxide film to which a heat treatment was applied and which covers an inner surface of the trench such that the trench is not filled with the first oxide film, and (c) a second oxide film covering the first oxide film therewith such that the trench is filled with the second oxide film, the first and second oxide films being on a level with a surface of the semiconductor substrate.
For instance, the first oxide film has a thickness smaller than a half of a width of the trench.
It is preferable that the shallow trench isolation further includes a third oxide film sandwiched between an inner surface of the trench and the first oxide film.
It is also preferable that the shallow trench isolation further includes a nitride film sandwiched between the third oxide film and second oxide film.
It is also preferable that the first and second oxide films are comprised of a high-density plasma chemical vapor deposition (HDP-CVD) film, a tetraethylorthosilicate non-doped silicate glass (TEOSNSG) film, a O3-TEOSNSG film, a high temperature oxide (HTO) film, or a spin on glass (SOG) film.
For instance, the semiconductor substrate is a silicon substrate, the first oxide film is a silicon dioxide film, the second oxide film is a silicon dioxide film, the third oxide film is a silicon dioxide film, and the nitride film is a silicon nitride film.
There is further provided a shallow trench isolation including (a) a semiconductor substrate formed at a surface thereof with a trench, (b) a first oxide film to which a heat treatment was applied and which covers an inner surface of the trench such that the trench is not filled with the first oxide film, and (c) a second oxide film to which a heat treatment was applied and which covers the first oxide film therewith such that the trench is filled with the second oxide film, the first and second oxide films being on a level with a surface of the semiconductor substrate.
The advantages obtained by the aforementioned present invention will be described hereinbelow.
In accordance with the present invention, recesses are not formed at a surface of an oxide film filling a trench therewith. Hence, it is possible to prevent deterioration in performances of a device, caused by the recesses, and also prevent generation of a stress in the semiconductor substrate.
The above and other objects and advantageous features of the present invention will be made apparent from the following description made with reference to the accompanying drawings, in which like reference characters designate the same or similar parts throughout the drawings.